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pci_config_hdr(9s)
NAME
pci_config_hdr - PCI: Contains configuration and register layout
information
SYNOPSIS
___________________________________
Member Name Data Type
___________________________________
vendor_id u_short
device_id u_short
command u_short
status u_short
rev_id u_char
class_code struct class_code
cache_line_size u_char
latency_timer u_char
hdr_type u_char
bist u_char
bar0 io_handle_t
bar1 io_handle_t
bar2 io_handle_t
bar3 io_handle_t
bar4 io_handle_t
bar5 io_handle_t
cis_ptr io_handle_t
sub_vendor_id u_short
sub_device_id u_short
exp_rom_bar io_handle_t
intr_line u_char
intr_pin u_char
min_gnt u_char
max_lat u_char
config_base io_handle_t
private u_long
___________________________________
MEMBERS
vendor_id
Specifies a vendor ID. The PCI bus configuration code obtains this
vendor ID from the vendor ID device register. This ID identifies
the manufacturer of the device that operates on the PCI bus.
Manufacturers who are members of the PCI special interest group
(SIG) can request a vendor ID to avoid conflict with other vendors.
device_id
Specifies a device ID that identifies the specific device. The PCI
bus configuration code obtains this device ID from the device ID
device register. The device's manufacturer determines its device
ID.
command Specifies a command that provides general control over a device's
ability to generate and respond to PCI bus cycles. The PCI bus
configuration code obtains the command from the command device
register. The PCI bus configuration code can set the command device
register, as represented in the command member, to the bitwise
inclusive OR of the command device register bits defined in
/usr/sys/include/io/dec/pci/pci.h.
status Records status information for PCI bus-related events. The PCI bus
configuration code copies this status information from the status
device register to the status member. Reads to the status device
register behave normally, but writes are handled specially. Some
bits may not be set by a write. For instance, most error bits are
designated as W1C (write 1 to clear). That is, whenever data is
written to the register, those register bits are cleared that
correspond to those data bit positions that are set. No other
register bits are affected by the write. The status device register
bits are defined in /usr/sys/include/io/dec/pci/pci.h.
rev_id Specifies a device-specific revision ID. The PCI bus configuration
code obtains this device-specific revision ID from the revision ID
device register. The device's manufacturer determines its revision
ID.
class_code
Specifies a class code. This member is a data structure that stores
information related to the device's class code device register.
cache_line_size
Specifies a cache line size in units of 32-bit words. The PCI bus
configuration code obtains this cache line size from the cache line
size device register. Power-on self-test code sets the
cache_line_size member according to PCI Local Bus Specification
Revision 2.1.
latency_timer
Indicates the value of a bus master's latency timer in units of PCI
bus clock ticks. The PCI bus configuration code obtains this
latency timer from the latency timer device register.
hdr_type
Identifies a multifunction device and specifies the layout of bytes
16 through 63 in the configuration space header. The PCI bus
configuration code obtains this information from the header type
device register.
bist Controls and records the status of a device's built-in self test.
The PCI bus configuration code obtains this value from the built-in
self test device register.
bar0 Contains an I/O handle to the address space specified by the base
address zero (BAR0) device register. A driver can read the I/O
handle from the bar0 member and use it in calls to the read_io_port
and write_io_port routines to access the address space.
bar1 Contains an I/O handle to the address space specified by the base
address one (BAR1) device register. A driver can read the I/O
handle from the bar1 member and use it in calls to the read_io_port
and write_io_port routines to access the address space.
bar2 Contains an I/O handle to the address space specified by the base
address two (BAR2) device register. A driver can read the I/O
handle from the bar2 member and use it in calls to the read_io_port
and write_io_port routines to access the address space.
bar3 Contains an I/O handle to the address space specified by the base
address three (BAR3) device register. A driver can read the I/O
handle from the bar3 member and use it in calls to the read_io_port
and write_io_port routines to access the address space.
bar4 Contains an I/O handle to the address space specified by the base
address four (BAR4) device register. A driver can read the I/O
handle from the bar4 member and use it in calls to the read_io_port
and write_io_port routines to access the address space.
bar5 Contains an I/O handle to the address space specified by the base
address five (BAR5) device register. A driver can read the I/O
handle from the bar5 member and use it in calls to the read_io_port
and write_io_port routines to access the address space.
cis_ptr Points to the Card Information Structure (CIS) for a CardBus card.
This read-only register contains an offset to where the CIS begins
in configuration space, memory space, or expansion ROM space.
sub_vendor_id
Specifies a subsystem vendor ID. The PCI bus configuration code
obtains this subsystem vendor ID from the subsystem vendor ID
device register. This ID identifies the manufacturer of a device
that operates on the PCI bus from the same controller card as other
devices with the same vendor and device IDs. The device's
manufacturer determines its subsystem device ID.
sub_device_id
Specifies a subsystem device ID that identifies the specific
device. The PCI bus configuration code obtains this subsystem
device ID from the subsystem device ID device register. This ID
identifies a device that operates on the PCI bus from the same
controller card as other devices with the same vendor and device
IDs. The device's manufacturer determines its subsystem device ID.
exp_rom_bar
Contains an I/O handle to the address space specified by the
expansion ROM base address device register. A driver can read the
I/O handle from the exp_rom_bar member and use it in calls to the
read_io_port and write_io_port routines to access the address
space.
intr_line
Specifies interrupt routing information for a PCI bus device. This
member may or may not indicate to which input of the system
interrupt controllers the device's interrupt pin is connected.
Device drivers use the ihandler_id_t key returned from the
handler_add routine to enable, disable, and delete an interrupt
service routine in the operating system.
intr_pin
Determines the mapping of handler_add calls to system interrupt
request line logic.
min_gnt Specifies a minimal time period for which the device requires a bus
grant. The min_gnt member stores a value that specifies how long a
burst period the device needs. The period of time is expressed in
units of 1/4 microseconds.
max_lat Specifies maximum latency information. The max_lat member stores a
value that specifies how often the device needs to gain access to
the PCI bus. The period of time is expressed in units of 1/4
microseconds.
config_base
Provides an I/O handle to the base of a PCI bus device's
configuration address space. The driver can use this I/O handle in
calls to the read_io_port and write_io_port routines.
private Specifies a private storage area that the device driver can use for
storing driver-specific data.
DESCRIPTION
The pci_config_hdr data structure contains information that describes
configuration and device register layout information for each device
connected to a controller that operates on a PCI bus.
FILES
<io/dec/pci/pci.h>
SEE ALSO
Data Structures: pci_config_hdr(9s)
Manuals: Writing PCI Bus Device Drivers
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Index for
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Alphabetical
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